1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches used in forming contacts for ultra-scaled semiconductor devices.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FINFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FINFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FINFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
For FINFET devices, it is desirable to have a source/drain contact strap over an active region (Rx) to make sure all FINs are connected by contact. For example, as shown in the exemplary current art device 10 of FIG. 1, TS 12 straps over each FIN 14A-N to make sure even at a worst condition of misalignment, TS 12 will still provide adequate coverage. To avoid a gate contact (CB) 18 to TS 12 short due to insufficient distance D2 with a worst-case misalignment, current art device 10 has to position CB 18 of gate 20 a long distance D1 away from Rx 16. Although this prevents the CB to TS short, it is not desirable for circuit area scaling. Therefore, what is needed is a solution to at least this deficiency of the prior art.